Fault simulation measures or estimates the percentage of potential defects in a circuit that could be detected by a test applied to the circuit, by simulating the test applied to the circuit. A test comprises applying a set of stimuli (e.g., sine waves or digital patterns) to a circuit (e.g., an amplifier or logic gates), measuring parameters of the circuit's signals (e.g., input signal amplitude, output signal amplitude, or delay), analyzing the measurements to produce parameter values (e.g., gain equals output signal amplitude divided by input signal amplitude), and comparing each parameter of interest to lower and/or upper test limits to decide pass or fail.
The circuit under test (CUT) comprises circuit elements, each of which may be a capacitor, resistor, inductor, transistor, diode, or other passive or active electronic component. The CUT functions may be primarily digital, primarily analog, or mixed-signal, a mixture of analog and digital functions. Typically, digital circuits do not contain capacitors or resistors that have been designed intentionally into them, but to some extent any digital circuit can be regarded as being analog since all circuits are subject to parametric variations. This disclosure discusses mostly analog and mixed-signal circuits but is also applicable to digital circuits. A defect is usually understood to be an unintended physical change in a circuit caused by an unintended aspect of a manufacturing process. A fault is usually understood to be an unintended behavior of a circuit, such as a circuit node stuck at a constant voltage. For simplicity, this disclosure will use the terms defect and fault interchangeably.
In analog fault simulation, typically a defect-free version of a CUT netlist (a listing of the circuit's elements and its interconnecting nets or nodes) is tested using a transistor-level simulator such as SPICE. Then the CUT netlist is tested with a potential defect (e.g., a short circuit between two nodes of the circuit) injected. If the latter produces a test result different from the former, the defect is declared as detected. The simulation is repeated for each defect in a list of potential defects. Some defects are more likely than others; for example, a manufacturing process might be more susceptible to short circuits between adjacent nodes than to open circuits in connectors.
A definition for a test's fault coverage is the probability or likelihood of the CUT failing a test given that the circuit is defective. One way of measuring this is to calculate the percentage of potential defects that can be detected by the simulated test, divided by the total number of potential defects simulated. A more accurate calculation weights each potential defect by its relative likelihood of occurring.
Faults in a digital fault simulation are typically modeled as a logic input or output stuck at logic 1 or stuck at logic 0; the fault may be caused by a random defect that forms a short circuit between a logic gate's input or output and a power rail, or by an open circuit that causes an input's node voltage to drift to one of the two logic values.
Faults in analog fault simulation are usually split into two groups: hard faults that change the topology of a circuit, caused by random defects that form short circuits between nodes or open circuits in connections between elements; soft faults that change a parametric value of a circuit, for example its capacitance or resistance, caused by random or systematic process variations.
During circuit design, it is common to have multiple types or levels of netlists for a circuit, and for subcircuits of the circuit. Typically, the design intent is captured in a schematic drawing, like that in FIG. 1a. A text netlist, like that in FIG. 1b, is generated from the schematic by software so that the circuit's operation can be simulated using a transistor-level simulator. This is referred to as a design-intent netlist.
When simulation is successful, possibly after multiple iterations of the design, high-level behavioral or simplified models of subcircuits of the circuit are sometimes created to facilitate faster simulation of the whole circuit. A corresponding netlist is referred to as a model netlist. A model netlist can be considered a level higher than a design-intent netlist.
Eventually, a layout, like that in FIG. 1c, is created for the circuit, in which the different circuit elements are graphically arranged, a netlist, like that in FIG. 2b, is extracted by software, using the design-intent netlist for guidance, and a resulting extracted netlist (referred to as a physical-implementation netlist) contains the design-intent elements as well as parasitic elements such as parasitic capacitances between adjacent connectors, and parasitic resistances and inductances within connections between nodes. The physical-implementation netlist can be considered the lowest level of netlist. FIG. 2a shows a parasitic resistance R2 and a parasitic capacitance C2 added to the schematic of FIG. 1a, and FIG. 2c shows where those parasitic elements, R2 and C2, were extracted from in the layout.
A CUT netlist may be hierarchical, containing subcircuits, like the netlist in FIG. 3; the subcircuits may contain subcircuits, each of which contains subcircuits, and so on. A subcircuit may have one instance in the CUT or multiple instances, and each subcircuit may have one or more of the levels of netlists described.
To perform an analog fault simulation of a CUT, one method, as shown in FIG. 4, includes a step of altering the design-intent netlist of the CUT by injecting, one at a time, short circuits between the source and drain, then source and gate, and then drain and gate of each MOS transistor, and then injecting open circuits in the source, then the drain, and then the gate of each MOS transistor, resulting in six defects per MOS transistor, as shown graphically in FIG. 5. The step also includes injecting, one at a time, an open circuit in each resistor, capacitor, and inductor, and then a short circuit across each of them, resulting in two defects per element. After each defect is injected, the CUT and its test are simulated—if the test fails, the test is deemed to have detected the fault; if the test passes the defect is undetected. In a last step, the fault coverage is calculated as described earlier.
Advantages of the above method are that the layout netlist is not needed, which is useful because often it is not available, and in any case, a design-intent netlist simulates much faster than the corresponding layout-extracted netlist because the extracted netlist includes a large number of parasitic capacitances, resistances, and (less commonly) inductances. A shortcoming of this method is that the proximity of each circuit element in the layout is ignored, so circuit nodes that are adjacent to one another in the layout, hence more likely to have a short circuit defect between them, might not be simulated with this short circuit defect injected. A method that overcomes this shortcoming includes a step that graphically analyzes the layout to find where circuit nodes are more likely to be short circuited or open circuited. A method that avoids graphical analysis includes a step that injects defects in the layout-extracted netlist: resistances are increased to relatively high values to model open circuits, and short circuits are modeled as low value resistances connected across capacitances. The closer two connectors are to one another, the larger the parasitic capacitance between them will be. The longer and narrower a connection is, the higher its parasitic resistance will be.
Injecting an open circuit is not trivial. For many circuits, especially those including MOS transistors, a transistor-level simulator cannot simulate it if a portion of the circuit is entirely isolated from the rest of the circuit by the open circuit because the voltage between them becomes undefined. For example, if the gate of an MOS transistor is connected to nothing, its voltage may be undefined and hence whether the transistor conducts current is undefined. One method to prevent this undefined condition is to insert a high resistance (e.g. 1 gigaohm) resistor instead of a truly open circuit. Such a resistor, however, will have no effect on the DC voltage of the gate in a simulation if the resistor is connected between the gate and a DC voltage. This is a very common scenario in analog circuits like operational amplifiers that have DC bias voltages. Also, such a resistor is not very realistic since a truly open-circuit in a connection to a transistor gate would likely result in the gate being charged to a high or low voltage during the IC manufacturing process.
Another method for analog fault simulation of a CUT includes a step of varying parameter values (for example, capacitance, resistance, or transistor threshold voltage) of each element in the CUT and of all elements in the CUT, one parameter at a time, or using Monte Carlo selection of random values to vary multiple parameters simultaneously. Advantages of this method are that it is well suited to analog circuits, placement of elements in the layout is ignored, and it has been shown that any test that detects all parametric faults also detects all shorts and opens. Disadvantages of this method are that there are an infinite number of parameter variation combinations possible.
CUT netlists that have been generated from a design-intent schematic of the CUT do not contain any layout proximity or connector length information, thus the more-likely shorts and opens are difficult if not impossible to predict, as can be seen for the parasitic capacitor C2 shown in FIG. 2. Simulating all possible shorts is generally impractical and pointless—for 100 nodes there are 100×99/2=4950 possible two-node connections, many of which might be impossible. Simulating all possible opens is more practical—if there are 20 two-port elements (e.g. resistors) and 40 three-port elements (e.g. transistors), then there are no more than 20×2+40×3=160 possible opens.
Fault simulation time is a key obstacle to practical analog fault simulation of industrial circuits. Transistor-level simulation time for industrial mixed-signal circuits can range from minutes to days. The layout-extracted netlist of such a circuit may contain tens of thousands of parasitic capacitances and resistances, and hence potential defects. Using these netlists for defect-injection can require an equally large number of simulations. Relaxing the accuracy of a simulation may reduce simulation time but could make it difficult to distinguish a test that fails due to simulation inaccuracy from a test that fails due to detecting an injected defect. Simulating a random sample of defects may not simulate some of the most likely defects. Using the design-intent netlist of a circuit for fault injection may mean that some of the most likely defects are not injected for simulation: shorts between adjacent conductors, and opens in long, narrow conductors.
It is desirable to have a method for injecting defects that permits faster transistor-level fault simulation without relaxing simulation accuracy.
It is desirable to have a method that uses layout information, when it is available, so that more-likely defects are injected, but that uses the design-intent netlist when the layout is not available since that is a common case and typically simulates faster.
It is desirable to simulate variations in design-intent circuit elements since such a simulation inherently evaluates whether a test can detect shorts and opens that are not explicitly injected, but to not simulate variations in parasitic circuit elements since there are many more of them and even very large variations in their values typically have little or no effect on circuit performance.